Indian Institute of Technology Indore

IIT Indore

Hardware Security of DSP hardware

Hardware Security of DSP hardware

Embedding the Digital Signature

  1. ■ The additional constraints represented by the digital signature are embedded in the design during the register allocation step of high-level synthesis.
  2. ■ Register allocation step in HLS can be performed through creation of colored interval graph. The nodes of the CIG represent storage variables and an edge between two nodes indicates overlapping lifetime of those two storage variables in a particular control step.
  3. ■ Having an edge between two storage variables of a colored interval graph indicate that a common register cannot be allocated for storing two storage variables. To embed obtained digital signature in the register allocation step, additional constraints are added in the form of extra edges between nodes in a colored interval graph.
  4. ■ These additional edges added as digital signature constraints (representing watermark), ensures that the corresponding storage variables of a colored interval graph are forced to execute through distinct registers, affecting design datapath interconnectivity and architecture  

 

                                                 

PUBLICATIONS:

·         Anirban Sengupta, Mahendra Rathor "IP Core Steganography for Protecting DSP Kernels used in CE Systems", IEEE Transactions on Consumer Electronics (TCE), Volume: 65 , Issue: 4 , Nov. 2019, pp. 506 – 515

·         Anirban Sengupta, E. Ranjith Kumar, N. Prajwal Chandra "Embedding Digital Signature using Encrypted-Hashing for Protection of DSP cores in CE", IEEE Transactions on Consumer Electronics (TCE), Volume: 65, Issue:3, Aug 2019, pp. 398 – 407 

·         Anirban Sengupta, Deepak Kachave, Dipanjan Roy "Low Cost Functional Obfuscation of Reusable IP Cores used in CE Hardware through Robust Locking", IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems (TCAD), Volume: 38, Issue 4, April 2019, pp. 604 – 616 

·         Anirban Sengupta, Dipanjan Roy, Saraju P Mohanty, "Triple-Phase Watermarking for Reusable IP Core Protection during Architecture Synthesis", IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems (TCAD), Volume: 37, Issue: 4, April 2018, pp. 742 - 755